The present invention relates to a core voltage discharge driver.
In a memory device such as a dynamic random access memory (DRAM) device, a unit cell generally includes one transistor and one capacitor in which electric charges are stored as data. Since the capacitor formed on a semiconductor substrate is not fully electrically insulated from other components, the stored electric charges are discharged. That is, due to generation of a leakage current, data stored in the unit cell can be damaged. Accordingly, the memory device performs refresh operation periodically in order to maintain charges stored in the capacitor.
Changing internal addresses by itself, the memory device having a refresh mode performs the refresh operation in response to an external command. When the memory device enters the refresh mode in response to the external command, row addresses are increased in order and word line of corresponding memory cells is selected. A sense amplifier amplifies charges stored in the corresponding memory cells and the amplified charges are restored. The data stored in the memory cell is retained through the refresh operation.
The memory device generates a voltage required by internal components using a predetermined external voltage. In a DRAM device including a bit line sense amplifier, cell data is sensed using a core voltage. When a word line is activated, data stored in a plurality of memory cells, which are connected to the activated word line, are transferred to a pair of bit lines and the bit line sense amplifier senses and amplifies the voltage difference between the bit lines.
In order to store data in memory cells of the DRAM device, the bit line sense amplifier applies data on a bit line and a complementary bit line using the core voltage and thus the capacitor of the memory cell is charged. A core voltage driver generates the core voltage. As the operating speed of the DRAM device is increasing, the memory cell should operate more rapidly, so that more rapid charging of the capacitor is required. Thus, an overdriving method may be used. According to the overdriving method, instead of the core voltage, an external voltage higher than the core voltage is used at the time when the bit line sense amplifier consumes a maximum operation current.
When the DRAM device is driven, thousands of bit line sense amplifiers start to operate at the same time. The driving time of the bit line sense amplifier is determined depending on whether a sufficient operation current for driving it can be supplied. However, due to drop of an operation voltage according to the tendency of the low power consumption, it is difficult to supply a sufficient amount of the current at a time. In order to solve this problem, an overdriving structure for the bit line sense amplifier has been adopted. That is, in an initial operation of the bit line sense amplifier, a voltage higher than a normal voltage (a core voltage) is instantaneously applied to a voltage line RTO of the bit line sense amplifier.
FIG. 1 is a circuit diagram of a conventional driver for controlling overdriving of a bit line sense amplifier.
Referring to FIG. 1, the bit line sense amplifier 10 is connected between a pair of bit lines BL and BLB, and a voltage line RTO and a voltage line SB are connected to the bit line sense amplifier 10.
A core voltage VCORE is generally supplied to the voltage line RTO, but in initial operation, a power supply voltage VDD higher than the core voltage VCORE is supplied to the voltage line RTO in order to perform a sensing operation more quickly. The core voltage VCORE is supplied to the voltage line RTO when an NMOS transistor MN2 is turned on in response to a normal driving control signal SAP2 of the bit line sense amplifier 10, and the power supply voltage VDD is supplied to the voltage line RTO when an NMOS transistor MN1 is turned on in response to a overdriving control signal SAP1 of the bit line sense amplifier 10.
The voltage line SB is connected a ground voltage (VSS) terminal through an NMOS transistor MN3.
A precharge unit 20 is enabled in response to a control signal BLEQ to precharge the bit lines BL and BLB.
The above-described driver for controlling the overdriving of the bit line sense amplifier 10 activates a particular word line (not shown). Then, a plurality of cell transistors connected to the activated word line operates and data stored a plurality of memory cells connected to the activated word line are transferred to the bit lines BL and BLB.
The NMOS transistor NM1 is turned on in response to the overdriving control signal SAP1 for driving the bit line sense amplifier 10 and the NMOS transistor NM3 is turned on in response to a control signal SAN. Thus, the power supply voltage VDD is supplied to the voltage line RTO and a ground voltage VSS is supplied to the voltage line SB. In this way, the power supply voltage VDD and the ground voltage VSS are supplied to the bit line sense amplifier 10, the bit line sense amplifier 10 senses and amplifies a voltage difference between the bit lines BL and BLB.
When the bit lines BL and BLB are developed by the bit line sense amplifier 10, a voltage supplied to the voltage line RTO is changed from the power supply voltage VDD to the stable core voltage VCORE. That is, when the overdriving control signal SAP1 transits to low level, the normal driving control signal SAP2 transits to high level to turn on the NMOS transistor MN2 and the power supply voltage VDD is replaced with the core voltage VCORE.
However, in the conventional driver for controlling the overdriving of the bit line sense amplifier 10, the core voltage (VCORE) terminal and the voltage line RTO are connected to each other via the NMOS transistor MN2. Therefore, electric charges transferred from the power supply voltage (VDD) terminal to the voltage line RTO increases the core voltage VCORE.
Accordingly, in a conventional method, in order to prevent the increase of the core voltage VCORE a core voltage discharge driver is used to discharge to the ground voltage (VSS) terminal the electric charges transferred from the power supply voltage (VDD) terminal to the voltage line RTO as illustrated in FIG. 2.
FIG. 2 is a circuit diagram of a conventional core voltage discharge driver. In the core voltage discharge driver, the op-amp OP1 receives a reference voltage VRERC and a half core voltage HALF. In a discharge driving unit, an NMOS transistor MN6 discharges a core voltage VCORE in response to an output signal DRV_CLAMP of the op-amp OP1. Dividing resistors R1 and R2 divide the core voltage VCORE to generate the half core voltage HALF. The half core voltage HALF is inputted to the op-amp OP1.
A muting unit for muting the output signal DRV_CLAMP of the op-amp OP1 in response to an inversion signal of a clamp signal CLAMP is disposed between an output terminal of the op-amp OP1 and the gate terminal of the discharge driving unit. The muting unit includes an inverter IV1 and an NMOS transistor MN5. The inverter IV1 inverts the clamp signal CLAMP. The NMOS transistor MN5 is turned on in response to an output signal of the inverter IV1. The source terminal of the NMOS transistor MN5 is connected to a ground voltage (VSS) terminal. The op-amp OP1 is connected between a power supply voltage (VDD) terminal and the ground voltage (VSS) terminal. An NMOS transistor MN4 is connected between the op-amp OP1 and the ground voltage (VSS) terminal to open and close a current path between the power supply voltage (VDD) terminal and the ground voltage (VSS) terminal. The NMOS transistor MN4 is turned on in response to the clamp signal CLAMP.
The core voltage discharge driver discharges electric charges, which are transferred from the power supply voltage (VDD) terminal, to the ground voltage (VSS) terminal. That is, when the clamp signal CLAMP is in high level, the NMOS transistor MN4 is turned on to activate the op-amp OP1. The inverter IV1 inverters the clamp signal CLAMP of high level to turn off the NMOS transistor MN5. An output signal DRV_CLAMP of the op-amp OP1 is inputted to the discharge driving unit.
Dividing resistors R1 and R2 divide the core voltage VCORE to generate the half core voltage HALF, which is inputted to the op-amp OP1. The op-amp OP1 compares the half core voltage HALF with the reference voltage VREFC. When the half core voltage HALF becomes larger than the reference voltage VREFC, the output signal DRV_CLAMP of the op-amp OP1 increases and thus the NMOS transistor MN6 for discharge is turned on to decrease a level of the core voltage VCORE.
FIG. 3 is a circuit diagram of a conventional core voltage generator.
Referring to FIG. 3, in the core voltage generator, the op-amp OP2 receives a reference voltage VRERC and a half core voltage HALF. A driving unit includes the PMOS transistor MP2 that receives the output signal DRV_ACT of the op-amp OP2 as a gate input to generate a core voltage VCORE. Dividing resistors R3 and R4 divide the core voltage VCORE to generate the half core voltage HALF, which is inputted to the op-amp OP2. The op-amp OP2 is connected between a power supply voltage (VDD) terminal and a ground voltage (VSS) terminal. An NMOS transistor MN7 is connected between the op-amp OP2 and the ground voltage (VSS) terminal to open and close a current path between the power supply voltage (VDD) terminal and the ground voltage (VSS) terminal. The NMOS transistor MN7 is turned on in response to an active signal ACT.
A PMOS transistor MP1 is connected between the output terminal of the op-amp OP2 and the gate terminal of the driving unit, and is turned on in response to the active signal ACT. When the PMOS transistor MP1 is turned on, the power supply voltage VDD is inputted to the gate terminal of the driving unit.
In the above-described core voltage generator, when the active signal ACT is in high level, the NMOS transistor MN7 is turned on to activate the op-amp OP2. The PMOS transistor MP1 is turned off in response to the active signal ACT of high level and the output signal DRV_ACT of the op-amp OP2 is inputted to the gate terminal of the driving unit.
Dividing resistors R3 and R4 divide the core voltage VCORE to generate the half core voltage HALF, which is inputted to the op-amp OP2. The op-amp OP2 compares the half core voltage HALF with the reference voltage VREFC. When the half core voltage HALF becomes less than the reference voltage VREFC, the output signal DRV_ACT of the op-amp OP2 decreases and thus the PMOS transistor MP2 is turned on to increase a level of the core voltage VCORE.
FIG. 4 is a timing diagram of a conventional core voltage discharging operation and core voltage generating operation. Referring to FIG. 4, in the core voltage discharge driver, as the output signal DRV_CLAMP of the op-amp OP1 increases, the core voltage VCORE decreases and the core voltage generator of FIG. 3 begins to operate. Thereafter, the core voltage VCORE increases due to the operation of the core voltage generator.
Referring to a period A of FIG. 4, in a part of the period A, the output signal DRV_CLAMP of the op-amp OP1 is in high level and the output signal DRV_ACT of the op-amp OP2 is in low level. At this time, in the core voltage discharge driver electric charges are discharged from the core voltage VCORE terminal. On the other hand, in the core voltage generator electric charges are supplied from the power supply voltage (VDD) terminal to the core voltage VCORE terminal.
Since the size of the PMOS transistor MP2 serving as the driving unit is larger than the size of the NMOS transistor MN6, the core voltage VCORE increases, but unnecessary current is consumed in the period A. In addition, due to decrease of the level of the core voltage VCORE, operation of the driver may be unstable.